For example, a power amplifier used in a wireless communication apparatus, such as a mobile terminal, on a transmitting side handles signals (i.e., modulated waves of digital signals) that have been subjected to digital modulation such as amplitude modulation or phase modulation. As such, the power amplifier requires improvement in linearity of an output signal, i.e., a reduction in distortion.
In addition, the power amplifier requires a reduction in power consumption, i.e., high-efficiency of power amplification in order that the life of a battery provided in the wireless communication apparatus can be prolonged.
A reduction in distortion of a power amplifier can be achieved through Class A operation of a transistor of an output block in the power amplifier.
However, a wireless communication apparatus including a Class A power amplifier has a larger electric current, while receiving no signal (so-called idle current), than a wireless communication apparatus having a Class B power amplifier.
Therefore, a wireless communication apparatus having a Class A power amplifier consumes a large amount of power, thereby having a difficulty in achieving low power consumption.
For this reason, an art is dominantly adopted in which a power amplifier of a wireless communication apparatus allows a transistor of its output block to carry out Class A operation and Class B operation, i.e., the transistor of the output block to carry out Class AB operation so that the low power consumption is achieved.
In general, a gain of a Class A power amplifier can be maintained nearly constant until an output power comes close to a saturated output power of the power amplifier.
In contrast, generally, a gain of a Class AB power amplifier greatly fluctuates depending on an increase in output power. This greatly impairs linearity of the Class AB power amplifier, in contrast to a Class A power amplifier.
In a case where power amplification of a digitally-modulated signal is carried out by a Class AB power amplifier having impaired linearity, a spectrum of an output power of the power amplifier becomes broad. This is not desirable since the output power having a broad spectrum serves as a disturbing wave with respect to a channel adjacent to a target channel.
In view of the circumstances, a conventional power amplifier is disclosed in Patent Literature 1 (Japanese Unexamined Patent Application Publication, Tokukai No. 2002-84144 A (Publication Date: Mar. 22, 2002)), as a power amplifier whose aim is to carry out highly efficient power amplification with low distortion.
The power amplifier disclosed in Patent Literature 1 adopts the art below in order to prevent impairment of linearity of a power amplifier in which the transistor of the output block performs Class AB operation.
FIG. 13 is a diagram illustrating a circuit configuration of the power amplifier disclosed in Patent Literature 1.
According to the power amplifier illustrated in FIG. 13, a distortion compensating circuit (regulator circuit) 21 in which a resistor 4 and a capacitor 5 are connected in series is connected, via a variable impedance element 2, to a base terminal of a bipolar transistor 102 (hereinafter, referred to as “transistor 102”) for signal amplification-use which follows a bipolar transistor 101 (hereinafter, referred to as “transistor 101”) for signal amplification-use.
Specifically, the base terminal of the transistor 102 is connected to one end of the variable impedance element 2. The other end of the variable impedance element 2 is connected to one end of the resistor 4. The other end of the resistor 4 is connected to one end of the capacitor 5. The other end of the capacitor 5 is grounded.
The power amplifier illustrated in FIG. 13 further includes a supply voltage terminal 1, a DC regulator element 22 having a resistor 3, the transistor 101, an input terminal 103, an output terminal 104, an input matching circuit 105, an interblock matching circuit 106, an output matching circuit 107, two supply voltage terminals 108, and a supply voltage terminal 109.
In the power amplifier illustrated in FIG. 13, a base bias point of the transistor 101, which is not subjected to distortion compensation made by the distortion compensating circuit 21, is set to a base bias point of a transistor which carries out Class A operation or Class AB operation close to Class A operation.
On the other hand, in the power amplifier illustrated in FIG. 13, a base bias point of the transistor 102, which is subjected to distortion compensation made by the distortion compensating circuit 21, is set to a base bias point of a transistor which carries out Class B operation, or Class AB operation close to Class B operation.
The transistor 101 performs Class A operation or Class AB operation close to Class A operation. Therefore, the transistor 101 has a characteristic in which a gain is reduced when an input power increases close to a saturated output power of the transistor 101.
On the other hand, the transistor 102 performs Class B operation or Class AB operation close to Class B operation. Therefore, the transistor 102 has a characteristic in which a gain is increased when an input power increases close to the saturated output power of the transistor 102.
Thus, the transistors 101 and 102 exhibit nearly opposite distortion characteristics of output powers with respect to input powers, respectively. This allows the power amplifier, as a whole, to cancel out distortions caused by the transistors 101 and 102.
As a result, the power amplifier disclosed in Patent Literature 1 allows an improvement in distortion characteristic of an output power with respect to an input power.
A degree, to which the distortions are cancelled out, can be adjusted through an adjustment of a resistance of the resistor 4 and/or a capacitance of the capacitor 5. The resistor 4 and the capacitor 5 are included in the distortion compensating circuit 21 which serves as a part of a bias circuit for the transistor 102. The bias circuit is a circuit for supplying a predetermined bias current (base bias point) to the base terminal of the transistor 102. The bias circuit is composed of the distortion compensating circuit 21, the variable impedance element 2, and the DC regulator element 22.
With the arrangement, Patent Literature 1 realizes a power amplifier that is low in power consumption and low in distortion (i.e., small in gain deviation with respect to an output power).
Unfortunately, the problem arises that it is likely to decrease the saturated output power of a power amplifier, in a case where the power amplifier is configured based on the disclosure of Patent Literature 1 so as to have a highly efficient low-distortion characteristic.
The below describes the problem, with reference to FIG. 13.
A saturated output power of the power amplifier illustrated in FIG. 13 depends on an output impedance of the bias circuit. Note that the output impedance is an output impedance of the bias circuit which is obtained when the bias circuit is viewed from the base terminal of the transistor 102, which serves as an output block.
In a case where an output impedance of the bias circuit is high, in general, a voltage drop occurs at the base terminal of the transistor 102 due to the output impedance when the base current increases in response to an increase in input power. The voltage drop causes a decrease in base voltage of the transistor 102. Accordingly, an output power of the transistor 102 decreases. As a result, a gain of the output block of the power amplifier decreases, thereby causing a decrease in saturated output power.
As such, it is preferable to minimize an output impedance of the bias circuit in order to prevent (i) a decrease in base voltage of the transistor 102 and (ii) a decrease in saturated output power of the power amplifier illustrated in FIG. 13.
An impedance Zb of the bias circuit of the power amplifier illustrated in FIG. 13 is expressed by the following equation (1):Zb=Zc+Zd  (1)where an impedance of the supply voltage terminal 1 is infinity; an impedance of the variable impedance element 2 is represented by Zd; and an impedance of the distortion compensating circuit 21 is represented by Zc.
The impedance Zc of the distortion compensating circuit 21 is equal to an impedance of a series circuit in which the resistor 4 having a resistance Rc and the capacitor 5 having a capacitance Cc are connected in series.
In order to minimize the impedance Zb of the bias circuit, it is necessary to minimize the impedance Zd of the variable impedance element 2, and to minimize the impedance Zc of the distortion compensating circuit 21. In order to minimize the impedance Zc of the distortion compensating circuit 21, ideally, the resistance Rc of the resistor 4 is set to 0 and the capacitance Cc of the capacitor 5 is set to infinity.
Note, however, that the power amplifier should cancel out the distortions caused by the transistors 101 and 102 so as to have a highly efficient low-distortion characteristic. On this account, the distortion compensating circuit 21 should be adjusted so that the resistance Rc of the resistor 4 and/or the capacitance Cc of the capacitor 5 to have specific optimum value(s).
Therefore, it is difficult to simultaneously optimize a saturated output power and an amplitude distortion.